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RESEARCH
HIGHLIGHTS |
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Project |
Dopant extraction using scanning capacitance
microscopy.
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Description:
Continual scaling of devices into the deep-submicrometer
regime has resulted in the need for two-dimensional (2-D)
dopant profiling with nanometer spatial resolution. There
are many dopant profiling techniques available currently,
but these are essentially one-dimensional methods, e.g.
secondary ion mass spectroscopy (SIMS) and spreading
resistance profiling. The objective of this project is to
develop an accurate 2-D dopant profiling method with high
spatial resolution using scanning capacitance microscopy (SCM)
measurements. Inverse modelling using the MEDICI device
simulation program has been carried out for dopant
extraction from measured SCM data using a p-n junction test
sample. The results were calibrated (compared) using SIMS
data. [Appl. Phys. Lett., vol. 80, no. 25, p. 4837, 2002.].
We are currently investigating the sensitivity of the SCM
measurements on the quality of the overlying oxide layer on
the test sample and the effects of the tip geometry.
Contact Person:
A/Prof WK Chim
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Project |
Growth, Characterization and Interconnection of
Nanostructures. |
Description:
This project aims to develop techniques to make
interconnects to nanostructures, ranging from traditional
techniques, to more novel techniques using field emission
induced growth recently developed at NUS. With the nanowire
growth technique, we have already demonstrated the ability
to grow sub-10 nm metallic wires on carbon nanotubes, and we
aim to generalize, control, and automate the technique to
wire nanostructures to external electrodes. We will also
grow and explore the properties of a variety of nanotubes
and nanorods grown via CVD and VLS processes. This project
will provide us with the capability to grow, characterize,
connect and study the electrical behaviour of
nanostructures.
Contact Person:
A/Prof JTL Thong
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Project: |
Investigation of Ultra Thin Oxide Properties and
its Influence in CMOS ULSI Integrated-Circuits.
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Description:
Today, the state-of-the-art CMOS Integrated Circuit
technology in the industry has 0.18 micron channel length
with the gate oxide as thin as 4 nm. It is predicted that a
gate oxide thickness of thinner than 3nm will be needed for
MOS transistors with a channel length below 0.1 micron. High
quality ultra thin oxide becomes one of the bottle-necks for
developing the next generation ULSI technology. In this
research project, we intend to find the deeper understanding
of the ultra thin oxide properties, the new characterization
method and new test standard in evaluating the oxide
property and lifetime, and to develop new process
technologies to form highly reliable gate oxide layer,
including the formation of nitride oxide and
nitrogen-profile engineering in ultra-thin gate oxide. The
influence of ultra-thin oxide properties in designing low
power ULSI circuit systems will also be investigated.
Contact Persons:
Prof MF Li
and
A/Prof BJ Cho
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Project: |
Low-frequency noise characterisation of
interconnect reliability.
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Description:
Advancements in technology have resulted in aggressive
down-scaling of device and interconnect dimensions in
integrated circuits (ICs). This has resulted in several
reliability concerns in thin films used in interconnects and
various applications. Examples of such reliability issues
are electromigration, stress-induced migration and voiding.
One of the first applications of noise measurement for
detecting metal film defects was carried out by Vossen (Appl.
Phys. Lett., 1973). Subsequent works have shown the
viability of using low-frequency noise measurements for
detecting electromigration-induced damage. Our work so far
has indicated the feasibility of using low-frequency noise
measurements for void parameter extraction in aluminum alloy
and copper interconnects; such voids could be the result of
electromigration or electrostatic discharge (ESD) induced
damage. A void-extraction algorithm using combined
low-frequency noise and resistance measurement has been
developed [J. Electronic Materials, vol. 30, no. 12, p.
1513.]. Most of the noise measurements so far have been
conducted at moderately high current densities of about 5
MA/cm2. To conduct the noise measurements at lower current
densities that are closer to those encountered under normal
operating bias, a more sensitive ac-bridge/lock-in detection
setup has been developed and is currently being refined to
optimize its performance. This will help in the development
of an accurate and robust void parameter extraction model
and also to understand the sensitivity of the noise
measurements to void shape, void size, stress and other
parameters.
Contact Person:
A/Prof WK Chim
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Project: |
Nanocrystal growth, characterization and
application in memory devices. |
Description:
The increasing use of portable electronics and embedded
systems has resulted in the need for low-power high-density
nonvolatile memory devices. Nanocrystal memories, utilizing
dimensional scaling of the floating gate to attain
observable room temperature threshold voltage shifts upon
charge injection and storage, can satisfy such a need. Over
the past years, we have carried out research on the
formation of germanium (Ge) nanocrystals embedded in silicon
oxide synthesized by sputtering and rapid thermal annealing
and demonstrated the charge storage effect [Appl. Phys. Lett.,
vol. 80, no. 11, p. 2014, 2002.]. We have managed to control
the size and vertical ordering of the nanocrystals and have
also acquired a bit more understanding of the charge storage
mechanism in the nanocrystal structures [To appear in Appl.
Phys. Lett., vol. 81, no. 19, 2002.]. We are currently
investigating the possibility of using such nanocrystal
devices for flash memory application. To achieve
controllable device characteristics, we are looking at ways
to manipulate the arrangement or spatial order of the Ge
nanocrystals. We are currently investigating various
methods, such as the use of a template mask during Ge
sputtering, to achieve lateral spatial ordering of the Ge
nanoparticles. This is a collaborative project with staff
from the Microelectronics Laboratory and the Singapore-MIT
Alliance.
Contact Persons:
A/Prof WK Chim and
A/Prof WK Choi
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Project: |
Near IR
Spectroscopic Photon Emission Microscopy for Deep Submicron
Devices.
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Description:
Detection of electroluminescence using Photon Emission
Microscope(PEM) is a useful technique in the fault
isolation. Spectroscopic analysis of photon emission yields
additional information on the nature of the emission, which
is correlated to the defect mechanism. Furthermore,
increasing use of flip chip technology renders the frontside
of the device unaccessible, and the silicon substrate is
transparent to light with wavelengths longer than 1100nm.
This project aims to build a spectroscopic detector to study
the emission from devices at wavelengths from 800nm to
1550nm. Low energy emission from deep submicron devices are
studied to extract further information, which is yet
observed in visible spectroscopic PEM.
Contact Persons:
Prof JCH Phang and
Prof DSH Chan
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Project: |
Next Generation Technologies for Semiconductor
Inspection and Defect Review.
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Description:
The feasibility and profitability of the semiconductor
manufacturing industry has always hinged on the premise of
making products with high throughput, leading-edge feature
geometries and high yield targets. It is well-recognised
that the real throughput bottlenecks in the manufacturing
process lies not in the front-end processing, but rather in
the quality assessment defect-tracing and failure analysis
cycles. At present, these primarily image-based procedures
still rely heavily on the competence of the human operator,
with the attendant disadvantages of relatively low
throughput, high cost and potential for human error. Hence,
it is highly-desired that the cycle times for these
fault-finding procedures be continually reduced in other to
minimise line down times and also achieve high accuracy of
the process at reasonable cost. A strategy that appears to
hold much promise is to exploit advances in computing
algorithms and hardware performance to incorporate ever
higher degrees of computer-based analysis and
instrumentation control in order to overcome existing
application issues.
Contact Person:
Dr.
WK Wong
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Project |
Novel Electron Sources. |
Description:
This project aims to develop and study novel field-emission
sources for electron-optical instrumentation. The electron
sources are characterized in a custom-built UHV system
equipped with an energy analyzer. Nanowire field-emitters of
tungsten and carbon grown by a field-emission induced
process have demonstrated remarkable stability. In
collaboration with the Physics Department, we are also
studying the field-emission characteristics of novel metal
oxide nanostructures grown by a simple hotplate technique.
Contact Person:
A/Prof JTL Thong
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Project: |
Oxide reliability under high field impulse
stressing and application to nonvolatile semiconductor
memory device and reliability characterisation.
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Description:
There is a trend towards the use of shorter duration pulses
and shorter time-between-pulses for the programming of
nonvolatile semiconductor memory (NVSM) devices. Pulse
duration of 100 ns or smaller has been used for programming
of flash and nanocrystal memory devices. Oxide degradation
under high field impulses is therefore of particular
interest in NVSMs that use tunnelling for the programming of
the memory cell. Previous work has shown the increased
sensitivity of low-frequency noise measurements for the
detection of latent damage in oxides subjected to high field
impulse stressing [IEEE Electron Device Lett., vol. 19, no.
10, p. 363, 1998; Jpn. J. Appl. Phys., vol. 40, no. 12, p.
6670.]. The various defect generation and conduction
mechanisms responsible for the stress-induced leakage
current (SILC) in thin oxides have been investigated [J.
Appl. Phys., vol. 91, no. 3, p. 1304 and 1577, 2002.].
Studies were also conducted to understand the trap
generation and relaxation processes occurring during high
field impulse stresses. An experimental setup for studying
the charge storage, charge retention, write/erase endurance
and read disturb characteristics of NVSMs has been developed
and used for investigating the reliability of NVSMs under
high field impulse stressing. The setup is currently being
used for the characterisation of germanium nanocrystal
memory devices that are fabricated in-house.
Contact Person:
A/Prof WK Chim
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Project: |
Photon emission microscopy of biased MOS devices.
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Description:
This project involves the use of the photon emission
microscope for studying the electroluminescence from biased
MOS devices. Past studies have used the in-house developed
setup for investigating the electroluminescence from MOS
devices under hot-carrier biasing conditions. A gated photon
counting method has also been developed to measure the weak
electroluminescence from silicon dioxide. The experimental
setup is currently being used to investigate the
electroluminescence from germanium nanocrystal structures.
Contact Person:
A/Prof WK Chim
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Project: |
Quantum mechanical (Q-M) modelling and
characterisation of thin gate oxide and alternative high-k
gate dielectrics.
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Description:
Aggressive reduction of device feature sizes has led to MOS
devices with gate oxide thickness of less than 5 nm and
substrate doping approaching 1018 cm-3. Accurate
characterisation (e.g., capacitance-voltage C-V and
current-voltage I-V) of such devices will require the
modelling of the quantum-confined 2-D electron charges
tunnelling into the gate oxide. A Q-M program has been
developed for oxide thickness extraction and tunnelling
current calculations by solving Poisson's and Schrodinger
equations self-consistently. It is predicted that silicon
dioxide as a gate dielectric will reach its minimum
thickness limit of about 2 nm because of the increasing
dominance of the direct tunnelling gate leakage current for
such thin oxides. Various high-k dielectric materials (e.g.,
hafnium oxide, zirconium oxide and their silicates) have
been identified as potential replacements for silicon
dioxide. Work is currently being carried out to fabricate
and characterise test structures with the high-k gate
material. The Q-M program has also been modified for
extracting the equivalent-oxide-thickness (EOT) and also for
investigating the current conduction in the high-k
dielectric devices.
Contact Person:
A/Prof WK Chim
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Project: |
Scanning Electron Acoustic Microscopy for Subsurface
Microelectronic Inspection & Failure Analysis.
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Description:
The
current project (in collaboration with Qualcomm Inc. USA)
explores the application of SEAM to the non-destructive
detection of subsurface features such as voids, cracks and
delaminations in semiconductor devices including those using
copper/low-K interconnect structures. It is desireable
that a non-invasive diagnostic capability be available for
the detection of buried features prior to employing
destructive and time-intensive procedures such as delayering
and cross-sectioning of suspect samples that can also induce
delamination and cracking that can be misinterpreted as
failures. In addition to serving as a flag for the
presence of defects, this work also aims to develop further
understanding on the complex physical interactions in the
formation of signal contrast in SEAM imaging of
semiconductor samples.
Based on a scanning electron microscope (SEM), the contrast of the SEAM
technique uses the bulk electromechanical properties of the sample due to the
electro-thermal-acoustic signal generation mechanism. Hence, the technique is
sensitive to sample parameters such as thermal conductivity, acoustic impedance,
Young’s modulus, electrostriction effects, local piezo and ferroelectricity that
do not normally produce contrast in conventional electron-beam inspection. The
technique also extends the information-gathering capabilities of the SEM into
the deep subsurface regime (up to a few ten’s of microns) for thermal
wave-related signal generation mechanisms, compared to the micron range of
current high-energy backscattered electron and X-ray analysis. Additionally,
the options of either frequency-derived or time-resolved detection modes provide
a means for spatially localizing areas of interest in the Z-axis, thus giving
the added potential of depth-profiling or tomography capabilities to the
technique. However, much of these operation modes are still not
well-understood and hence require further research into the signal contrast
mechanisms which are extremely sample-dependent.
Contact Person:
Dr WK Wong
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Project: |
Scanning Thermal Microscopy for Integrated
Circuit Failure Analysis.
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Description:
Due to the shrinking feature sizes of modern devices, the
exact localization of these defects using established
thermal failure analysis becomes difficult. The near field
Scanning Thermal Microscopy (SThM) is a recently developed
Scanning Probe Microscope (SPM) technique that detects
specimen thermal features. This project aims to build a SThM
for the failure analysis of integrated circuits. This
technique will give information about the temperature
distributions of the device with a temperature resolution of
a few milliKelvins as well as other thermal properties like
thermal conductivity in the nanometer scale. It will also
provide an understanding of the heat generation mechanism.
Different types of devices will be investigated.
Contact Person:
Prof JCH Phang
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